CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis

High-Level Synthesis (HLS) allows to synthesis un-timed behavioral descriptions into efficient RTL (Verilog or VHDL). Although much progress has been made to improve the quality of HLS it is often reported that the generated RTL code from HLS leads to larger circuits as compared to hand optimized Verilog or VHDL. To measure the gap between hand optimized RTL and automatically generated RTL from HLS, periodic studies are presented were the authors manually optimize designs in RTL, re-write the functionality in C and then compare the quality of the generated RTL code. This is useful, but not very scalable as it is only possible to do this for a small number of designs. Moreover, the result from HLS is highly dependent on the synthesis options used, typically in the case of HLS, these have the form of pragmas (comments) that allow to control how to mainly synthesize arrays (e.g., RAM or registers), loops (e.g., unroll, partially, not unroll) and functions (e.g., inline or not). To address this, in this work we present an RTL to C compiler that generates synthesizable C code for HLS combined with an auto-tuner to automatically find HLS constraints such that the generated RTL code from HLS is as close as possible in terms of area and performance to the original manually optimized RTL code. This allows to directly compare the quality of the generated RTL code by further synthesizing these into equivalent gate netlist.