A 61 mHz - 3.4 Hz High-pass Capacitively Coupled Analog Frontend with Tunnelling Biasing and Output DC Servo Loop

In this paper, a low-power capacitively coupled analog frontend with programmable high-pass cutoff frequency from 61 mHz to 3.4 Hz is proposed. The DC operating point of the input differential pair is settled by dynamic equilibrium of direct tunneling current. A DC servo loop (DCSL) based on duty-cycled operational transconductance amplifier (DC-OTA) has been implemented at the output nodes of the main frontend so that its impedance will not be affected. A minimum of 1.67 pA/V effective transconductance has been realized through the DC-OTA techniques in DCSL, which enable the frontend to achieve 61 mHz high-pass cutoff frequency with only a 10 pF on-chip capacitor. The frontend is implemented in standard
$\mathbf{0.18}- \mu \mathbf{m}$
CMOS process and it consumes
$\mathbf{2.72} \ \mu \mathbf{A}$
current in total, achieving a noise efficiency factor of 6.01 in 25 kHz bandwidth (61 mHz - 25 kHz).