Cryogenic Hysteresis in 110 nm Bulk Silicon MOSFETs for Capacitorless Memory Applications

In this letter, we characterize the commercial 110 nm bulk silicon MOSFETs down to 6 K, with a focus on cryogenic capacitorless memory applications. The substrate-induced steep subthreshold swing (SS) and hysteretic loop are observed at low temperatures. At 6 K with
${V}_{\text {D}}$
= 1.8 V, the minimum SS is
$\boldsymbol { < }0.3$
mV/dec and the hysteretic loop is
$\boldsymbol {>}\, 0.2$
V wide with a
$\boldsymbol {\sim }10 \boldsymbol {^{{8}}}$
ratio of high to low drain current states. For the first time, we demonstrate the cryogenic capacitorless memory operation of bulk silicon MOSFETs. It shows a
$\boldsymbol {\sim }12 \boldsymbol {\mu }\text{A}$
sense margin, long retention time (on the scale of minutes when T
$\boldsymbol {\leq }\, 30$
K), and high write and read endurance. These features make it promising as a compact capacitorless single-transistor memory for low-temperature applications.