FPGA Implementation of Non-Commensurate Fractional-Order State-Space Models

In order to obtain a general-purpose real-time simulator that can handle actual analog input and output for a linear time-invariant (LTI) fractional-order system, and also be suitable for MIMO and non-zero initial-state start-up LTI fractional-order systems, this paper presents a method for designing a real-time hardware simulator of non-commensurate fractional-order state-space model (NCFO-SSM) based on FPGA. The numerical approximation of NCFO-SSM for FPGA implementation is given to enhance computing efficiency and reduce the computational complexity of the NCFO-SSM systems. The FPGA implementation of NCFO-SSM is then established to achieve the hardware simulator design of a general purpose for LTI fractional-order systems. To further balance the relationship between the accuracy and the occupancy of FPGA logic resources, a fractional-order Gr
$\ddot {\text {u}}$
nwald-Letnikov (GL) operator is proposed based on the piecewise quadratic equation fitting (PWQEF) method. Applications of the proposed PWQEF operator in the NCFO-SSM hardware simulator show that the new hardware simulator can achieve the closest results to theoretical computation. The proposed NCFO-SSM hardware simulator is used to implement fractional-order systems, including a fractional-order PID controller system, an MIMO system, and an H-bridge current source PWM regulator system, to further illustrate its application scope and practicability in LTI fractional-order systems.