Design, Implementation, and Power Analysis for Network-on-Chip Architectures

Network on Chip (NoC) architectures offer better scalability and performance compared to traditional bus-based interconnects, however low-power consumption in NoC architectures is an important concern that cannot be ignored as high power consumption can lead to increased operating costs, reduced battery life, and thermal management issues. In this work, two well-known NoC architectures such as 3×3 CLICHÉ and 3×3 TORUS architecture have been designed to achieve high performance with minimum power dissipation. The experimental work for designed architectures has been divided into two major parts for analysis. Firstly, the design has been simulated or tested using random input patterns that have been generated with different signal probabilities through the test bench. And secondly, the power of two NoC architectures has been estimated through the physical models, and comparison is done with a simulated tool. For an entire NoC, the total average power is extracted by the simple addition of dynamic and static power. In experimental results, the comparison shows that the total power consumed by the CLICHE architecture is low as compared to TORUS using fix number of Intellectual Property (IP) cores in the network. Also, the average maximum error is estimated to be 18.7 % for power estimation. This highlights the importance of verifying power consumption estimates through physical measurements and testing to ensure the accuracy of the results.