A Simulation Study On SSD PCB Warpage During Reflow: From Understanding To Improvement

Solid state drives (SSD) have become more and more important in high-performance computing and data centers. The demand for higher density and more advanced technology in SSD leads to more severe warpage risk during and after reflow that can cause issues for the device reliability, such as poor solder joint formation, joint cracking, die cracking, pad cratering. SSD PCB (printed circuit board) warpage, therefore, needs to be carefully controlled for processing, assembly and reliability purposes. Warpage is usually caused by Coefficient of Thermal Expansion (CTE) mismatch between the PCB and components as well as intrinsic stresses within the PCB during the reflow process. In this paper, a numerical method was developed to capture warpage in SSD PCB during reflow, and the simulation model was validated by test results. Two different approaches to tackle multi-layer PCB materials were introduced: smear layers with effective properties and trace mapping; “birth and death” technique was used in the model to mimic the reflow process. Many factors contributing to the warpage of the PCB assembly were studied: PCB board material properties, PCB board copper layer distribution, and component/die placement. Warpage of the PCB board at array level was also studied.