A Predictive Model of Wafer-to-Die Warpage Simulation

Wafer warpage has always been one of the most challenging issues in the fabrication of electronic devices. It causes many troubles for tools to handle the wafers during the manufacturing process. Also, wafer warpage directly links to die warpage then package warpage which play a key role in microelectronic reliability. To avoid any warpage-induced failures in electronic packaging such as crack and delamination, wafer and die warpage must be well understood and controlled. Therefore, a reliable numerical model to simulate the wafer fabrication process and to obtain step-by-step wafer warpage is very much needed. In addition, the process of wafer warpage translating into die warpage should be characterized. The work in this study shows a complete and straightforward simulation guideline from wafer warpage to die warpage. The simulation models were validated and correlated with test data.