Design and Implementation of Staggered-SAR Azimuth-Processing

New Synthetic Aperture Radar (SAR) Techniques to achieve high resolution, wide swath imaging like SCORE and Staggered-SAR require more complex onboard processing, compared to previous solutions. In this paper, a concept for implementing the azimuth processing required for Staggered-SAR is presented, and an implementation for a space-grade Field Programmable Gate Array (FPGA) is shown. Simulation shows that the necessary computational performance can be achieved, although memory constraints remain a concern. Investigations into the datarates for multi-beam SCORE dataprocessing are presented. A data management scheme is proposed and evaluated. It is shown that with the given system parameters the current limiting factor is the available on-chip memory. The effect may be mitigated through new innovative data handling schemes and data reduction strategies to yield the full beamforming performance.