Ultralow-Power and High-Speed In-Memory Computing Unit Based on Field-Accelerated Spin-Orbit Torque MRAM Utilizing Voltage-Controlled Magnetic Anisotropy

Spintronic-based in-memory computing (IMC) architectures have gained intensive attention as a potential solution to address the von Neumann bottleneck. In particular, the write-like in-memory logic paradigm via memory cells has been explored as an alternative to traditional computing architectures with complex sensing circuits and independent logic computing units. However, this approach suffers from the drawback of high write energy consumption compared to the conventional read energy consumption. In this article, we propose an ultralow-power, high-speed IMC unit based on field-accelerated spin-orbit torque (SOT) magnetic random access memory (MRAM) using voltage-controlled magnetic anisotropy (VCMA). We investigate the magnetization dynamics of the device by solving the modified Landau–Lifshitz–Gilbert equation using a physics-based compact model. The proposed MRAM is evaluated for Boolean-logic operations and nonvolatile full-adder (NVFA) under 28 nm process technology node using hybrid CMOS/MTJ simulations. Our results show that the proposed MRAM achieves a low write latency of 0.8 ns and low power dissipation of 2.804 fJ/bit. Additionally, it supports 1-bit NVFA operations of 13.0 ns and 25.2 fJ/bit. These findings suggest that the proposed MRAM can serve as a flexible and scalable IMC platform.