Design of High Noise Tolerant Single-Bit Line 8T SRAM Cell

This article presents a noise tolerant single bit line 8T SRAM (PROP8T) cell. HSPICE Monte Carlo Simulations are used to measure the critical design metrics of proposed 8T SRAM cell. Estimated results are compared with the conventional 6T (CONV6T) SRAM cell and Transmission Gate based 8T (TG8T) SRAM cell. The PROP8T has shown less read delay (TRA) than CONV6T and TG8T. The write delay (TWA) of PROP8T has improvement over 4x times on CONV6T and 1.2× times on TG8T. The proposed design also offers 3.1× and 2× improvement in read static noise margin (RSNM) on CONV6T and TG8T respectively. The proposed design layout occupies 1.08x lesser area as compared to TG8T but it occupies 1.66x larger area as compared to the CONV6T.