Even-Odd Sorting Network for Fast Binary Counters

In various digital signal processing devices, the efficiency of data multiplication is a common performance limiter and the critical route includes the parallel summing of multiple operands. Therefore, high compression is used to speed up the summation process. Binary counters with specific design are required to reduce some efficiency parameters in the partial products compared to traditional one’s counters. In this project, we introduce a technique for quickly saturated binary counters used to design multipliers. This method involves a design of a sorter network using different sorting algorithm that is "Even-Odd" sorting. By using this technique, (15,4) and (31,5) binary counters are designed and further optimization of the parameters are compared in terms of latency and area. These counters can be further implemented in8 × 8, 16 × 16 bit multipliers and area-delay product, powerdelay product values can be obtained. These sorter networks and design of binary counters are programmed and synthesized in Xilinx Vivado tool.