Comparative Analysis of FinFET and CMOS based Adiabatic ECRL Technique

Achieving low power consumption along with low delay for adiabatic logic circuits is challenging in CMOS technology. This study has presented an adiabatic Efficient Charge Recovery Logic (ECRL) technique based 2:1 MUX designed using FinFET 18 nm technology. A comparative analysis of the design has been performed with CMOS 2:1 MUX. Further parametric analysis of 2:1 MUX is performed in terms of average power dissipation, propagation delay, Power Delay Product (PDP), and Energy Delay Product (EDP) are presented in this work. All considered parameters have been analyzed for 0.5 V, 0.7 V, 0.9 V, and 1. 1V. The results show that the PDP of ECRL at 1.1V is $4.05\times 10^{-15}$J, at 0.9 V is $0.27\times 10^{-15}$J, at 0.7 V is $1.02\times 10^{-15}$J, and at 0.5 V is $0.51\times 10^{-15}$ J. While, the EDP at 1.1V is $0.15\times 10^{-22}$ Js, at 0.9 Vis $0.01\times 10^{-22}$ Js, at 0.7 Vis $0.03\times 10^{-22}$ Js, at 0.5 V is $0.02\times 10^{-22}$ J. The FinFET based 2:1 based ECRL is found to be energy efficient in contrast to CMOS based design. The ECRL technique base d2:1 MUX reported in this work may be used for biomedical applications in the future.