A Pixel-Level, High Dynamic, Low-Power, Digital-Readout-Integrated Circuit With Hybrid Analog-to-Digital Converter for Infrared Focal-Plane Arrays

This letter presents a pixel-level, high-dynamic-range, low-power, digital-readout-integrated circuit (DROIC) for infrared focal-plane array (IRFPA) who usually suffers from obvious leakage current and nonnegligible noise current. Nonfeedback-reset pulse-frequency-modulation (PFM) technology that with fewer
mosfet
s, adjustable transfer charge pumps, and pixel second-order hybrid quantization analog-to-digital converter (ADC) is employed to advance the linearity and reduce the power consumption of this DROIC. In addition, it is designed and simulated using a 180-nm one-poly six-metal CMOS process, with pixel pitch of 15
μ
m, effective number of 15.93 bits, linearity up to 99.60%, power consumption of 1.303
μ
w, and dynamic range of 100.2 dB.