Minimizing Quiescent Power in a Dynamically Biased Comparator and its Application in Relaxation Oscillator

This paper presents a dynamically biased, high-speed comparator architecture consuming a very low quiescent power. In conventional comparator topology, there is an underlying trade-off between the speed and the quiescent power consumption. The proposed comparator adopts a dynamic current boosting mechanism that momentarily provides a large amount of dynamic current near to the comparison point when both inputs of the comparator are getting close to each other. However, when those input voltages are widely separated, the proposed comparator enters to a low current state where the excess dynamic current has been reduced to minimize the quiescent power. To appreciate its benefits, a relaxation oscillator has been developed using the proposed comparator, targeting a nominal frequency of 1 MHz in 180 nm CMOS process. The simulation result shows that the quiescent power consumption of the proposed comparator has been decreased by ~6X as compared to the conventional fixed biased comparator while maintaining the same speed of operation. The quiescent power consumption of the relaxation oscillator has been decreased by >11X using the proposed comparator compared to the conventional one. This proves the effectiveness of the proposed technique.