Comparative Analysis of DCVSL and MDCVSL Techniques in 18nm FinFET Technology

In the VLSI design circuit, average power dissipation is a very common source of concern. This paper aims to reduce the average power dissipation and other parameters that are performed in this paper notably propagation delay, EDP (energy delay product), and PDP (Power delay product). These two technologies have been compared based on 2:1 MUX using Differential Cascode Voltage Switch Logic (DCVSL) and Modified Differential Cascode Voltage Switch Logic (MDCVSL) has been presented with FinFET 18nm technology. The results show values of Power Delay Product (PDP) and Energy Delay Product (PDP) for DCVSL based on 2:1 MUX using FinFET approach at different voltage levels notably at 1.2V is 1612.41× 10-15 (J), at 1V is 566.744× 10-15 (J) and at 0.8V is 198.177× 10-15(J). EDP of DCVSL at 1.2V is 4075.68×10-22 (Js), at 1V is 1431.36× 10-22 (Js) and 0.8V is 5047.9× 10-22 (Js) respectively. MDCVSL using 2:1 MUX has shown efficiency in terms of both EDP and PDP over DCVSL using 2:1 MUX PDP of MDCVSL at 1.2V is 1230.164× 10-15 (J), at 1V is 400.542× 10-15 (J) and at 0.8V is 137.716 × 10-15(J). EDP of MDCVSL at 1.2V is 3107.39× 10-22 (Js), at 1V is 1010.92× 10-22 (Js) and 0.8V is 3471.6× 10-22 (Js). In relation to the DCVSL approach, MDCVSL has evidenced an improved transient response and lower energy usage. Consequently, the MDCVSL is used in both industrial and biological uses, and it can be used for digital and cascading circuits.