The ID Instability Induced by Reverse Conduction Stress in p-GaN Gate HEMTs

In this work, the impact of reverse conduction stress on the output current (
${I} _{D}$
) instability in p-GaN gate HEMT are investigated. With more negative drain stress (
${V} _{\text {DS}, \text {str}}$
below −5 V), the
${I} _{D, \text {max}}$
shows a positive shift in the
${I} _{D} - {V}_{\text {DS}}$
measurement at
${V} _{\text {GS}}$
= 3 V and a negligible change at
${V} _{\text {GS}}$
= 5 V, meanwhile the
${V} _{\text {TH}}$
shows a negative shift after the stress. By contrast, the
${I} _{D, \text {max}}$
is basically unchanged with the
${V} _{\text {DS}, \text {str}}$
above −5 V. Through the simulation and extended experiments, it is found that the hole tunneling under the more negative
${V} _{\text {DS}, \text {str}}$
and the subsequent hole accumulation and trapping within the gate stack dominate the
${I} _{D, \text {max}}$
instability. The comparison of gate leakage and the transmission electron microscopy (TEM) observation before and after the stress further shows that the gate stack degenerates.