A Surface Potential Based Full-Region Current Model for Doping Segregated TFETs

A physics-based SPICE model for dopant segregated tunneling field-effect transistors (DS-TFETs) with gate-to-drain underlap is developed for the design technology co-optimization (DTCO) of TFETs with the foundry process. It captures all the current components in full operation regions, including band-to-band tunneling (BTBT), forward p-i-n diode, gate leakage, and also ambipolar conduction. The channel surface potential is formulated first, with which the current expressions are derived and verified with experiments calibrated TCAD simulations. Model predictions of current, conductance, and voltage transfer characteristic (VTC) are in good agreement with measurement data of hardware devices (nTFET and pTFET) as well as circuits. This model has been written in Verilog-A language and employed in the TFET circuits design.