In-house developed 32-bit Digital Signal Processor for Strategic Applications

Avionics systems rely on digital signal processing algorithms for various applications like Navigation, Guidance and Control, Image and Data Processing etc. Digital Signal Processors (DSPs) are typically used to implement these algorithms, which require intense iterative computations to be performed on large data sets. DSPs generally provide special addressing modes, dedicated hardware blocks and enhanced parallelism to meet the stringent timing requirements of these computations. Commercial DSPs are available in various ranges of capability and speed, however, their use in strategic applications is governed by their availability and reliability criteria. Usage of commercial DSPs is made difficult due to long lead times, obsolescence, import restrictions and cost. In this work, we present the architecture and design of a scalable 32-bit Floating point DSP, with an in-house developed architecture, instruction set, assembly language and software toolset. The DSP provides high performance in terms of fast execution, low overhead and interrupt latency, making it suitable for time critical DSP applications. The DSP also implements special instructions, called algorithmic instructions, which provide hardware acceleration for selected computation intensive operations. The performance of the DSP in executing commonly used signal processing algorithms compares well with commercial DSPs currently used in avionics systems. The design is currently implemented as a core in Field Programmable Gate Array (FPGA), making use of the internal memory blocks of the FPGA to hold program and data. Different versions of the DSP have been flown in various Satellite and Launch Vehicle avionics systems.