Research on Convolution Decomposition and Hardware Acceleration based on FPGA

Convolutional neural network (CNN) is an artificial intelligence algorithm with a wide application foundation. In recent years, to improve the computational speed of the computation-intensive CNN models, many researchers have accelerated hardware implementation on FPGA. However, the acceleration algorithms are mostly unfriendly to hardware or have poor flexibility, which leads to a decrease in computing power and an increase in data access. In this paper, we propose a convolution decomposition method in the time domain, which fully considers the behavior of convolution operation and the difference between data streams in hardware. Besides, we design a hardware acceleration architecture. The results show that this design can be compatible with convolution and full connection operations of various sizes and strides. Hardware tailoring and cascade expansion are proposed for different application scenarios. Experiments show that the computing performance per DSP is 0.39 GOP/s, which demonstrates that the hardware design has a better multiplier utilization than similar works.