High Gain Multistage CMOS Amplifier Design at 45nm technology node

Analog design is still a challenge for designer working at lower technology node due degradation in devices and circuit performance and increased short channel non ideal effects. Medical equipment needs a high gain low noise amplifier frequently in medical data acquisition and signal processing. CMOS differential amplifiers are suitable choice for designer due its high value of gain, noise margin and CMRR. Multiple stages of amplifiers further improve gain but at the cost other analog performance. Use of low and high VT transistors are preferred for the transistor connected to input signal and load respectively. Multiple stages of PMOS load are also improves the overall gain with the increase in number transistors. To achieve high gain self-bias operational transconductance amplifiers are suitable choice with higher W/L ratio of PMOS at output stage amplifier. In this paper, CMOS based high gain self-bias double-stage and triple stage amplifiers have been designed at 45nm technology node using Cadence Virtuoso. DC and transient analysis are carried out for performance evaluation to find suitable amplifier topology and circuit schematic.