FPGA Implementation of Area Efficient 16-Bit Vedic Multiplier Using Higher Order Compressors

The objective of this paper is to propose an 16-bit Vedic multiplier using higher order compressors. In Conventional multiplier, there are many partial steps which reduce the computational speed of a multiplier. Along with accuracy, the emphasis is on reducing processor area, power, and delay by increasing speed. Vedic mathematics rules and algorithms create partial products at the same moment, saving time. The performance of the multiplier in terms of latency, power, and area is found by the number of stages used to sum the partial products. In this paper, a novel Vedic multiplier architecture is presented that reduces area while increasing speed when compared to conventional Vedic multipliers. The suggested model is simulated and synthesized using Xilinx Vivado on different FPGA families and delay, area and power are observed. The conclusion drawn from observing the result is that implementation of multiplier using Virtex-6 (lower power) provides optimized outputs in terms of area, delay and power. The model is also implemented on Basys3 Artix7 FPGA with the help of Xilinx Vivado and verified the functionality of the proposed model.