An approach for modeling propagation delay of a subthreshold inverter incorporating DIBL effect

The paper investigates the impact of Drain Induced Barrier Lowering (DIBL) on the propagation delay of subthreshold CMOS inverters. The authors analyze the subthreshold behavior of the inverter using LTSpice simulations and show that the DIBL effect impacts the transistor characteristics and the circuit performance. The paper demonstrates that neglecting the DIBL effect leads to inaccurate estimates of the inverter propagation delay, which can cause errors in the circuit design. By considering the DIBL effect, the paper proposes a new model to accurately calculate the inverter propagation delay in the subthreshold region. The proposed model that takes into account the DIBL effect has been shown to accurately predict the propagation delay over a wide range of conditions and technology parameters.