Energy Efficient Double Tailed Cascaded Comparator for EEG Application

This brief shows the necessity of power consumption in a dynamic cross-coupled latch-based comparator. The proposed comparator is mainly designed using a cascading method that benefits in lowering power consumption as well as power delay product which is suitable to implement in EEG (Electroencephalogram) applications and in other cardiac IMD (Implantable Medical Devices). The latched comparator as analog to digital converter series a crucial function in terms of the amount of power consumed. This work presents a cascaded comparator circuit which is simulated at the CMOS technology node of 180nm using the Mentor Graphics Tool. The simulation result shows power dissipation 19.126$\mu$W at 0. 8V supply voltage and 19.19$\mu$W at 0. 6V supply voltage which is quite less as compared to the existing comparator circuits. In addition, the power delay product of the proposed comparator is 0. 383pJ when the supply voltage is 0. 8V, and it is 0.0384 when the supply voltage is 0. 6V.