Improving the fabricated Rate and Reliability of Top Gate a-IGZO TFTs under Positive Bias Stress by Using Double-Stacked Gate Insulator Layer Design

In this work, the top gate a-IGZO TFTs with double-stacked gate insulator (GI) layer are designed and fabricated. During the deposition of GI-1 and GI-2, GI-1 layer is fixed with the same SiH
4
flow, and the GI-2 layer is modulated with higher the SiH
4
flow. With this process design, the process rate of GI layer can be increased, and the reliability under positive bias stress (PBS) can be also improved without affecting the initial electrical characteristics of the devices, including threshold voltage (Vth) and subthreshold swing (SS), which means other process conditions do not need to be changed. The less right shift of Vth at the devices with higher SiH4 flow during the GI-2 layer deposition are observed under PBS. Results indicate that the GI-2 layer contains more amount of hydrogen, which diffuses into the GI-1 layer during the anneal process to reduce the defects, resulting in fewer electron trapping and less degradation under PBS.