Realization of High Performance Approximate Multipliers for FPGA Application

It is possible to use a variety of computer arithmetic systems to carry out a complex multiplier. The efficiency of an FPGA- VLSI processor relies on how quickly its digital signal processing operations can be carried out. In order to achieve both high accuracy and speed, the authors of this work offer a concept for a 64-bit approximation multiplier technique that utilizes compressors and partial product multipliers. For artificial intelligence (AI) based FPGA-VLSI applications, approximate multipliers are among the fastest multipliers available. The suggested study reveals a 64-bit approximation to a 64-bit multiplicator. To implementation of the proposed 64-bit digital approximate multiplier, we are using the partial product or dada based multiplication technique; in which the 64 bit multiplication process complete in the partial form. 64 bit split into the 32,16,8,4 and 2 bit multiplication. We are considering performance parameters in terms of the area, latency and PDP. The area is reducing up to 55%, latency and PDP is reducing approx. up to 70% then existing work. Proposed multiplier gives 99% accuracy. The FPGA integrated circuit utilized for the simulation is a member of the virtex 7 family.