Layout-Dominated Electro-Thermal Optimization for Multichip Power Modules with Response Surface and Fourier Series Model

The multichip high-power modules are critical components to realize power conversion in automotive powertrain and renewable energy. High power density tendency and extreme operation capability require the thermal optimization design for power modules. However, there is still a gap in the rapid electro-thermal evaluation and large-scale layout optimization for multichip parallel configuration. In this paper, a comprehensive layout-dominated electro-thermal co-design method is derived to optimize the multichip placement pattern. In the proposed method, the layout-dominated parasitic parameter is established by a hybrid method of analytic approximation modeling and response surface analysis, while the layout-dominated thermal performance is evaluated by a multilayer Fourier series method. Furthermore, the multichip power dissipation distribution is auto-solved by a set of frequency domain based electric circuit equations. Combined with the heuristic genetic algorithm optimizer, a novel successively staggered multichip layout pattern is consequently proposed and validated to achieve the current sharing and thermal balance without any additional components or advanced materials. The prototype experimental results demonstrate that the current imbalance ratio and maximum chip temperature are decreased by 50.3% and 18.1% respectively.