Design Guidelines to Reduce Parasitic Capacitance in Planar Inductors

Reduction of parasitic capacitance is essential for planar magnetics, like planar inductors, in high frequency applications to reduce displacement currents and capacitive losses. The parasitic capacitance in planar inductors has been studied by accurate physics-based analytical models. But state-of-the-art design guidelines to reduce parasitic capacitance are only derived for single stranded wire or litz wire inductors, which are not applicable for planar inductors because of different winding structure. Therefore, this paper proposes design guidelines to reduce parasitic capacitance in planar inductors. Firstly, physics-based analytical model of parasitic capacitance in planar inductor is built in detail. Then design guidelines are derived based on different independent variables in analytical model. In the end, the effectiveness of proposed design guidelines is verified by simulations and experimental tests.