PMOS Biased Sense Amplifier Using Cadence Virtuoso With gpdk 90nm Technology

Sense amplifiers are essential for the recital operation and dependability of the memory circuits. A sense amplifier biased by PMOS with a maximum output impedance, less power dissipation, and minimal sensing delay is the suggested design. In this study, we compared PMOS-biased sense amplifiers with a focus on power and stability. The performance of the sense amplifier was evaluated and simulated using Cadence Virtuoso. The sense amplifier circuit, created with Cadence Virtuoso with 180 nm technology, will use 80.05 nW of power. A similar sense amplifier circuit is designed in this work using the 90 nm library parameters in Cadence Virtuoso. By employing cadence virtuoso with 90 nm technology, the proposed sense amplifier circuit's power is reduced by up to 30.43 u W. In 180nm technology, we will receive 80.05 uW of power. By using 90 nm technology power will be reduced as compared to 180 nm technology.