Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects

As CMOS scaling has slowed down, high-performance computing has turned to 2.5D and 3D heterogeneous integration to simultaneously increase density and performance. Vertical die-to-die (D2D) interconnect standards are required to enable an ecosystem of 3D-stackable chiplets, as has been proposed in a draft AIB-3D specification [1]. In this paper, we make the case that vertical D2D interconnect standards must bridge a design space wider than has existed for horizontal interconnect, with wide-ranging implications on architectural specifications.