Circuit Reliability of $\text{MoS}_{2}$ Channel Based 2D Transistors

Inverters being the basic logic element of the circuits used, we have demonstrated
$\boldsymbol{\text{MoS}_{2}}$
-based inverter degradation in terms of various parameters (inverter high output (V
OH
), inverter low output (V
OL
), rise time
$\boldsymbol{(\mathrm{t}_{\mathrm{r}})}$
, gain) under critical stress conditions. These stress conditions include multiple voltage transfer characteristics (V
TC
) sweeps, application of
$\boldsymbol{10^{4}}$
pulses at the input of inverter (VIN), change of output dynamic response with continuous pulses, and long duration DC stress for logic 0 and 1 at VIN. The percentage degradation in inverter characteristics was found to be increasing with an increase in supply voltage (V
DD
) for all the stress cases. Among various stress cases run, V
OL
increased by 120 mV, V
OH
decreased by 150 mV, gain decreased by 500 mV/V, and
$\boldsymbol{\mathrm{t}_{\mathrm{r}}}$
increased by
$\boldsymbol{4 \mu\mathrm{s}}$
. The degradation in inverter key parameters was found to be originated from the deterioration in the performance of the individual driver and load transistors.