Physical Insights Into the ESD Behavior of Field Plated UHV LDMOS Devices

Field plates are commonly used to extend the breakdown voltage to achieve high voltage devices. But, the role of field plates in the ESD behaviour of these devices is still not addressed. This work provides physical insights into the ESD behaviour of field plated Ultra High Voltage Laterally Diffused Metal Oxide Semiconductor (UHV LDMOS) devices. UHV devices are simulated and compared using 3D TCAD simulations. For the first time, the role of field plates in ESD design aspects is investigated. This paper highlights the importance of each field plate (Gate Field plate (GFp), Source Field plate (SFp) and Drain Field plate (DFp)), exploring their individual roles. It was found that GFp and SFp play a significant role in improving the trigger voltage and holding voltage, while DFp is the sole reason for enhancing the failure threshold. Finally, a 3D device failure study is performed to support the theory drawn from 2D simulations.