High Performance VLSI Architecture of FIR Filter for Seismic Signal Processing

As a primary requirement, FIR filters(Finite Impulse response)used in real-time seismic alert systems are required to be low complexity, fast, and re-configurable. The CSE technique is commonly used to abate hardware complexity in digital FIR filters by decreasing logic operators and logic depths. In this paper, we present a new LO and LD minimization matrix grouped CSE algorithm that outperforms existing CSE algorithms. Additionally, the suggested design With low complexity and reduced truncation error, we developed a new biased-based rounding method that includes half units, as well as to lessen critical-path delay, use the cut-set retiming technique. This paper presents two hardware-efficient FIR filter topologies (I and II) that employ cut-set retiming, HUB rounding, and the canonical signed digit based MCSE algorithm. Additionally, architecture II implements a reconfigurable FIR filter in a hardware- efficient manner. FPGA and ASIC platforms are used to implement the architectures on the hardware side. Comparing the hardware implementation of proposed architectures, we mooted decrease of LOs, CPD, effective latency, area-delay product (ADP), and power- delay product using cutting-edge CSE- based architectures by a factor of 2 more than 35%, 47 %, 36 %, 34 %, and 29 %,respectively.In comparison to the counterpart.the reconfigurable architecture II has an approximately 46 %, 10 %, and 11 % less in PDP, ADP and CPD.