Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths

Bias Temperature Instability (BTI) and Hot-Carrier Degradation (HCD) are key aging mechanisms, frequently studied with transistor measurements or inverter-based (INV) Ring Oscillators (RO) measurements. However, large-scale digital circuits are typically manufactured with standard cells (such as logic gates). In a reliability simulation flow (e.g., SPICE-based standard cell characterization with degraded transistors), many assumptions about the standard cells have to be made (such as load capacitance, signal slews, uncertainty in aging models, etc.) and can lead to high simulation uncertainty. In this work, we propose to verify this standard cell characterization with standard cell oscillator measurements in silicon. For this purpose, we present the following novel contributions: 1) The first work with BTI and HCD measurements of heterogeneous oscillators (multiple different cell types in one RO) based on logic paths extracted from processors. 2) The first work exploring the impact of BTI and HCD on oscillators containing combinational standard cells, i.e. single cells incorporating multiple logic gates (such as And-Or-Inverter (AOI) cells and Or-And-Inverter (OAI)) and cells performing complex actions such as full-adders.