Circulating Current Mitigation in Parallel Inverters by Dynamic Carrier Changing Technique

In parallel inverter system, power semiconductor switches conduct both load current and circulating current, caused by voltage difference between the inverters, which is due to (i) unequal power levels, (ii) interleaved PWM (for load current ripple reduction), and (iii) asymmetries such as unequal dead-time and device parasitics/tolerances. The circulating current incurs additional loss and reduces lifetime of converters. In this paper, it is established that the circulating current is proportional to Common Mode Voltage Difference (CMVD) between the inverters, that occurs during unequal load-sharing and interleaving. To reduce the circulating current, a dynamic carrier changing modulation technique is presented in this paper, by changing the phase of the carriers, based on the modulation angle of the modulating signals. The advantage of proposed technique is reduction of circulating current without affecting the load current ripple offered by conventional modulation techniques. The proposed technique can also reduce the circulating current in case of equal and unequal power sharing, and also when operated with DPWM techniques. Simulation and experimental results are presented to validate the effectiveness of the proposed modulation scheme.