Substrate Biasing Effect in a High-Voltage Monolithically-Integrated GaN-on-SOI Half Bridge With Partial Recessed-Gate HEMTs

The physical mechanism of the substrate biasing effect (SBE) in a high-voltage monolithically-integrated GaN-on-SOI half bridge with partial recessed-gate high-electron-mobility transistors (HEMTs) is comprehensively analyzed by TCAD simulation. The SBE originates from the capacitive coupling of the buffer layer and the buffer traps, which can be effectively suppressed by the GaN-on-SOI platform with the top Si shorted to the source technology. The simulations show that the
${R}_{\text {ON}}$
of high side HEMT on the GaN-on-SOI platform with the top Si shorted to the source is
$0.223 {\Omega }$
and does not degrade with the bus voltage increase, while the
${R}_{\text {ON}}$
increases from 0.223 to
$0.900 {\Omega }$
for the case on GaN-on-Si platform when the bus voltage increases to 400 V. In addition, for GaN-on-SOI platform with the top Si shorted to the source of HEMTs, the crosstalk can be effectively suppressed and the self-heating effect does not aggravate. Moreover, the integrated half bridge on GaN-on-SOI platform with the top Si shorted to the source shows lower overshoot current, tail current and switching power consumption compared to the half bridge made of two discrete HEMTs on GaN-on-Si platform.