A 0.5 THz Passive Quadrupler in 65 nm CMOS

This paper presents a terahertz frequency quadrupler using an accumulation-mode antisymmetrical MOS varactor (ASVAR) for the first time. Frequency multipliers using field-effect transistors (FETs) suffer from poor efficiency above process fT/fmax. Varactor frequency multipliers with a significantly higher dynamic cut-off frequency are better alternatives. While conventional frequency multipliers mostly use III-V devices such as GaAs SBDs, ASVAR's low cost and easy integration with on-chip antennas and drive power amplifiers in the same process make it a better prospect for terahertz applications. The proposed quadrupler reaches a peak output Power of -19.9 dBm at 514 GHz, and a minimum conversion loss of 32.5 dB. The simulated 3-dB output bandwidth is 58 GHz. The quadrupler is designed using 65 nm CMOS process, which does not require DC power consumption.