Plasma Induced Charging Damage Causing MOS Device Reliability Lifetime Degradation Originating From Well Charging of a Technology With Deep Trench Isolation

Well charging from plasma processing induced charging damage (PID) is an important reliability failure mechanism, which is present for technologies with isolated well areas. It requires a comprehensive PID qualification during technology development for a solid definition of well charging antenna rules in the design manual, which can guarantee a robust product design. A literature review on the well charging topic indicates a lot of characterization work on technologies with triple well or deep n-well. In this work a process node with a 7.5 nm gate oxide and deep trench isolation is investigated. It is found out that the well charging causes a MOS transistor parameter drift and no increased gate oxide leakage currents, which were reported in most earlier investigations. The findings of this work are based on PMOS and NMOS test structures with various well areas and antenna sizes and three reliability stress methods, constant current gate oxide stress, hot carrier stress and negative bias temperature instability stress. The most significant conclusion is that the MOS transistor lifetime clearly decreases with increasing antenna area and/or with increasing well size, which was verified by all three different reliability stress types.