A Simulation-Based Design Approach for Optimized Performance of Cu-Mo-Cu Clips in High-Power Semiconductor Modules

Wirebond interconnects on power devices represent a substantial failure point during switching operations. Copper clip interconnects represent a promising alternative for increasing lifetimes and limiting the failures associated with aluminium wirebonds. However, the CTE mismatch between clip and power device has the potential to create an alternative reliability concern as the assembly as a whole is cyclically heated. A simulation based design approach is presented with the aims of mitigating stresses induced by CTE mismatch at the clipchip interconnect layer. Design considerations, based on the simulation results, are incorporated into part manufacture and procurement, with verification being presented by way of power cycling of clip parts.