PYNQ-Z2 Based Hardware Implementation of Delay-Aware SFC Placement in 5G Networks Using PSO

The Network Function Virtualization (NFV) technology is a widely growing and promising one that has huge impact in both industry level and academic curriculum. NFV paradigm concept virtualizes network architecture concept that has the dedicated hardware components of Network Functions (NFs) to provide better flexibility and better resource sharing to network operators. It is really challenging to efficiently place Virtual Network Function's directed graphs in such a dynamic environment, known as SFCs (Service Function Chains), dynamically allocate and update the required resources for underlying network topology. This paper presents a delay and location aware Particle Swarm Optimization (PSO)-based approach, to perform sequential SFC placement in an optimized way. This flexible allocation approach takes in the requirements in terms of throughput, latency and bit error rate, in addition to resource utilization and traditional connectivity. The proposed architecture is implemented on a PYNQ-Z2 board to calculate the efficiency. PYNQ framework is used because it supports software/hardware libraries and has codesign environment on Xilinx FPGA. The efficiency of resource allocation can be made better by exploring wide range of FPGA's hardware resources.