Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm

The Fast Fourier Transformation(FFT), as a high-efficiency algorithm of the Discrete Fourier Transform (DFT), is widely used in Digital Signal Processing (DSP) and wireless communication systems. These applications are error tolerant due to the channel noise or error correction modules. Approximate Computing has shown effectiveness and feasibility in these applications. However, most approximate units are designed case by case in previous works, which is low efficiency and difficult to find the optimal design. In this paper, a mantissa bit-width adjustment algorithm for floating-point (FP) FFT is proposed under specific accuracy requirements. With the proposed algorithm, the approximate 64 FP FFT achieved 50% area reduction and 70% power delay product (PDP) reduction compared to the exact design with a 60dB Signal-Noise Ratio (SNR) requirement, which is also at least 33% and 52% better than the previous approximate FP FFT. The proposed approximate FFT design is verified in the channel estimation module of a wireless communication system, which has a neglectable impact on the bit error rate (BER) performance of the system.