FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor

Stacked Nanosheet Transistor (SNST) is the potential candidate for the Digital, Analog, and RF application due to its better SCE, ON current and area footprint. This work performs 3D FEM calculation of SNST to RF properties analysis for Single Gate Contact (SGC) and Double Gate Contact (DGC). Effect of SGC & DGC analyzed on gate resistance (Rg) and capacitance (C
gg
) of the device, which limits the unity gain frequency (f
T
) and maximum frequency of oscillation (f
MAX
). Variation of Rg with the device parameters such as gate length, sheet width, thickness, sheet pitch, stack spacing, and number of sheets are analyzed. Effect of SGC and DGC on R
g
, C
g
, f
T
and f
MAX
explained. The Optimum number of sheets required for better RF FOM is calculated.