Design of Energy Efficient and Low Delay Posit Multiplier

This paper focuses on the hardware implementation of the Posit Multiplier unit. The Posit number system is an alternative to the IEEE-754 Floating point unit because it provides more accurate results over the same word size. The better dynamic range is achieved by combining regime bits (of run-time varying length) and exponent bits, known as the run-time-varying exponent component. The existing leading one detector uses a Multiplexer-based logic, accounting for more area and data path delay in the higher-order posit arithmetic units. An Adder-based Leading One Detector has been proposed to reduce the delay and area. The Proposed Posit multiplier uses the proposed LOD to extract the data bits from the posit data for any given posit data width (N), exponent size (ES), and regime size (RS), achieving less area and data path delay. The separate calculation of the final exponent and final regime results in further improvement in the area due to the reduction of adder size. We synthesized the posit multiplier units for 8-bit, 16-bit, and 32-bit and compared the results with the existing work. The synthesis results show that reduction in delay of 17.55% and an increase in the energy efficiency of 28.35%, respectively.