A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology

Data transfer between processor and memory hierarchy constrains throughput of applications like Convolutional Neural Networks (CNNs) due to Von-Neumann bottleneck. In-Memory Compute (IMC) bypasses this bottleneck and enables much higher throughputs at constrained power budgets. Mixed Signal IMC SRAM architectures involve multiple wordline selection to enhance throughput and energy efficiency. Consequently bitlines discharge to much lower levels than a conventional SRAM. Conventional Sense Amplifiers (SAs) associated with bitlines are designed to operate at high common mode voltage and their offset increases as common mode voltage is reduced. In this work, we propose a common mode insensitive SA (CMI-SA) that has offset and delay that are independent of common mode voltage. The CMI-SA proposed in this work has a 3-sigma offset of 20–25 mV and a output delay of 200ps across a common mode range of 0.4V to 1.2V in an industrial 65nm Low Standby Power (LSTP) technology.