An Efficient FPGA Implementation of the Multiplier-less LMS Adaptive Filter

The paper presents the FPGA implementation of multiplier-less LMS algorithm in low power CMOS process. Nowadays, the adaptive algorithms are widely used in many VLSI signal processing/image processing applications. The adaptive algorithms such as LMS, RLS, and NLMS are widely used in many digital signal processors. Hence, the designing of these algorithms must be in reduced amount of power and area utilization. Then only, it will perform well in applications such as system identifications, denoising, etc. Hence, the paper mainly focused on the designing of this LMS algorithm. The existing hardware implementation of this LMS algorithm consists of huge amount of power and area due to the presence of multiplier. Normally, the multiplier contains more power and area compared to other arithmetic elements like adder, subtractor, etc. So, the paper focused multiplier-less design of the LMS adaptive filter algorithm in FPGA devices. The practical implementation of the proposed design is carried on the Quartus II Altera platform and parameter measurements like power, area and delay are done to valid the proposed design.