A dynamic computational memory address architecture for systolic array CNN accelerators

Systolic arrays architecture is widely used as a hardware accelerator of convolutional neural networks(CNNs) due to its simplicity and effectivity of de-sign principles without requiring complex control and data flow. However, the amount of data storage and processing in this architecture increases exponentially as the complexity of algorithms for CNN increases, thereby limiting the overall accelerator efficiency. We demonstrated troublesome access conflicts raise in memory banks while storing input feature maps on the on-chip memory and the processing element(PE) loads the convolutional layer feature map, affecting the data supply speed. A dynamic computational memory address architecture according to the stride of the convolutional kernel of different input feature maps, was proposed to cope with access conflicts in the on-chip memory banks. This proposed model is capable of greatly reducing the number of memory access conflicts in the memory banks and optimizing the efficiency of the on-chip memory, which aims to reduce the data loading time and improve the bandwidth utilization of the on-chip memory. The computational simulation results confirmed that the storage access time of AlexNet, YOLO v3, and ResNet-50 decreases by 30.49%, 27.37%, and 18.46% respectively, only at the sacrifice of 10% additional cost in the hardware overhead.