A Parallel Prefix Modulo-(2q + 2q−1 + 1) Adder via Diminished-1 Representation of Residues

Diminished-1 representation of modulo-
$(2^{q} + 1)$
residues provides for delay-balanced adders for the popular moduli set
$\tau = \{ 2^{q},2^{q} \pm 1\}$
. Besides, conjugacy of moduli
$2^{q} \pm 1$
leads to efficient multiple-residue to binary conversion. Nevertheless, cardinality of
$\tau $
does not cover the required dynamic range of some applications that also require small
$q$
-values for gaining the desired arithmetic speed (e.g., convolutional neural networks). The recently proposed parallel prefix modulo-
$(2^{q} + 2^{q - 1} - 1)$
addition scheme provides for balanced performance with similar adder architectures for the moduli of doubly-wide
$\tau $
(i.e.,
$\tau _{2} = \{ 2^{2q},2^{2q} \pm 1 \}$
). Should there be a compatible adder for the conjugate modulo
$2^{q} + 2^{q - 1} + 1$
, the new moduli set
$\tau _{2}^{+} = \{ 2^{2q},2^{2q} \pm 1,2^{q} + 2^{q - 1} \pm 1\}$
can provide more than
$(8q - 3)$
bits of dynamic range, with equally fast adders as those of
$\tau _{2}$
, whose dynamic range is only
$6q$
bits. Therefore, we were motivated to propose the new modulo
$2^{q} + 2^{q - 1} + 1$
and its equally fast parallel prefix adder with compatible cost as of its conjugate modulo. This is actually achieved via diminished-1 representation of residues, where those in
$[1,2^{q} + 2^{q - 1}]$
are encoded as
$[{ 0,2^{q} + 2^{q - 1} - 1}]$
and a zero indicator bit is set for 0-valued residues. The VLSI simulation and synthesis results, especially for the common cases of
$q = 2^{p}$
, confirm the analytical evaluations regarding the balanced performance of the conjugate moduli
$2^{q} + 2^{q - 1} \pm 1$
.