30.5 A 95.3% 5V-to-32V Wide Range 3-Level Current Mode Boost Converter with Fully State-based Phase Selection Achieving Simultaneous High-Speed $\mathbf{V}_{\text{CF}}$ Balancing and Smooth Transition

DC-DC boost converters are widely used for various applications that require a high supply voltage, including solid-state drives (SSDs), LED drivers, etc. A multi-level (ML) boost converter (BST) with a high conversion gain (CG) and low voltage rating for switches (SWs) would be an ideal solution to regulate the high output voltage
$(\mathrm{V}_{0})$
[1–4]. However, in practice, ML converters suffer from a flying capacitor
$(\mathrm{C}_{\mathrm{F}})$
voltage
$(\mathrm{V}_{\text{CF}})$
imbalance due to the parasitic capacitance
$(\mathrm{C}_{\text{par}})$
and gate driving power
$(\mathrm{P}_{\text{GD}})$
, etc., which causes not only large conduction losses
$(\mathrm{P}_{\text{COND}})$
in the on-resistance
$(\mathrm{R}_{\text{ON}})$
of the SWs and the parasitic resistance
$(\mathrm{R}_{\mathrm{L}})$
of the inductor (L), but also a large overlap loss and damage to the SWs. For these reasons, a
$\mathrm{V}_{\text{CF}}$
calibration
$(\mathrm{V}_{\text{CF}}-\text{cal})$
technique is essential to the ML converter. In particular, unlike a ML buck converter, MLBST requires the faster
$\mathrm{V}_{\text{CF}}$
-cal because the
$\mathrm{V}_{\text{CF}}$
's reference voltage
$(\mathrm{V}_{\text{CF},\text{REF}})$
is
$\mathrm{V}_{0}$
which can vary abruptly. For the
$\mathrm{V}_{\text{CF}}$
balance, prior works [1], [2] adjusted the duration of the
$\mathrm{C}_{\mathrm{F}}$
charging and discharging phase
$(\phi_{\text{CH}},\phi_{\text{DIS}})$
using two mismatched duties
$(\mathrm{D}_{1},\mathrm{D}_{2})$
modulated by the calibration loop. However, that caused sub-harmonic oscillations in the inductor current
$(\mathrm{I}_{\mathrm{L}})$
, which enlarged
$\mathrm{P}_{\text{COND}}$
in
$\mathrm{R}_{\mathrm{L}}$
proportional to the frequency. In addition, the bandwidth (BW) limit of the
$\mathrm{V}_{\text{CF}}$
-cal loop by the
$\mathrm{V}_{0}$
control loop and the repetitive
$\phi_{\text{CH}}$
and
$\phi_{\text{DIS}}$
every cycle cause difficulty of immediate
$\mathrm{V}_{\text{CF}}$
·cal in the start-up (Fig. 30.5.1, top left). Since it can result in breakdown and reliability issues for transistors, it is hard to mass produce the MLBST. Moreover, for the stability of the
$\mathrm{V}_{\text{CF}}$
-cal loop, an additional compensator that uses bulky passive components is necessary. Another structure that does not depend on the
$\mathrm{V}_{\text{CF}}$
-cal loop was proposed, but it needed an additional capacitor and incurred a surge current with redistribution losses due to the repetitive capacitor hard charging [3] (Fig. 30.5.1, middle left). Meanwhile, in power converters, the current mode control (CMC) is preferred thanks to the fast dynamic performance, over current protection, etc. But it is hard to apply it to the MLBST because of the mode transition issue. In the 3-level (3L) BST, there are two operation modes, mode-1
$(\phi_{\mathrm{M}1})$
and mode-2
$(\phi_{\mathrm{M}2})$
. Prior CMC 3L converter changed the mode between
$\Phi_{\mathrm{M}1}$
and
$\phi_{\mathrm{M}2}$
by the forced mode selection signal intermittently every pre-determined period at the mode transition point
$(2\mathrm{V}_{\text{IN}}\approx \mathrm{V}_{0})$
[2]. This was subject t0
$\mathrm{V}_{0}$
fluctuation due to the DC offset of
$\mathrm{I}_{\mathrm{L}}$
between two modes (Fig. 30.5.1, bottom left). To solve the above issues, we propose the following: 1) a fully state-based phase selection (FSPS) technique which is capable of the fast
$\mathrm{V}_{\text{CF}}$
-cal, stable start-up, and smooth mode transition without the
$\mathrm{I}_{\mathrm{L}}$
sub-harmonics of the
$3\text{LBST};2$
) a comparator-based low-power
$\mathrm{C}_{\mathrm{F}}$
-charqinq and discharging phase selector (
$\mathrm{C}_{\mathrm{F}}$
-CDPS) that does not require an additional compensator, and simultaneously enables both real-time
$\mathrm{V}_{\text{CF}}$
sensing and calibration signal generation; 3) an adaptive slope generator (ASG) for optimal slope compensation and smooth mode transition in a wide I/O range of CMC.