Eight-bit Quantization for Super-Resolution Networks and Its Hardware Implementation

This work presents an 8-bit quantization scheme for super-resolution (SR) networks and its hardware implementation. Quantizing SR models to run in 8-bit is a non-trial task, frequently leading to non-negligible restoration performance degradation. To address the problem, we first present a quantization scheme that mitigates accuracy drop by effectively capturing the distributions of both weights and activations. Second, the proposed scheme is implemented using Verilog HDL and the design is synthesized on Synopsys Design Compiler using TSMC 65 nm library. Lastly, experimental results illustrate the effectiveness and efficiency of the proposed method.