A Novel RRAM-based FPGA architecture with Improved Performance and Optimization Parameters

FPGA is an integrated circuit that is designed by a designer and configured by hardware descriptive language. So, in FPGA, we can add some memory to store the data using RRAM. Resistive Random-Access Memory-based routing multiplexers enhance the characteristics of FPGA architecture. The circuit design characteristics of RRAM-based multiplexers can be identified by their delay parameters with change in input size when compared to SRAM implementations because it controls the set or reset process, and therefore it is electrical parameters. In proposed method is circuit optimization. The one-level RRAM- based multiplexers vary with input size and we used small-sized programming transistors in 1-Transistor 1-Ram based multiplexers. The programming transistors normally are in small size which is reliable for the best Product delay power. Also, RRAM multiplexers need a smaller footprint, and the reduction in the area could be more adequately great and the proposed architecture for the routing tracks needs to redefine the routing tracks. In this paper, we compared the various power consumption and optimization FPGA Architecture between RRAM and SRAM-based FPGA Architecture and the results outperformed our proposed RRAM method.