Plasma induced charging damage (PID) from well charging in a BCD technology with deep trenches causing MOS device reliability lifetime degradation

As part of a PID process qualification a comprehensive well charging characterization is presented with home well and remote well charging stress measurements on nMOS and pMOS transistors with various well areas and stacked antenna sizes. Based on a literature review, contrary to most previous studies on MOS device lifetime degradation, a drift in threshold voltage was observed on a 7.5nm gate oxide but no increased dielectric leakage currents before or after a diagnostic PID stress. The PID assessment included various reliability stresses: constant current stress (CCS), hot carrier stress (HCS) and negative bias temperature instability (NBTI) stress. From the analyzed data a proposal is given for preventive antenna rules.